HUB Floating Point for Improving FPGA Implementations of DSP Applications

Abstract

The increasing complexity of new digital signal processing (DSP) applications is forcing the use of floating point (FP) numbers in their hardware implementations. In this brief, we investigate the advantages of using half-unit biased (HUB) formats to implement these FP applications on field-programmable gate arrays (FPGAs). These new FP formats allow for the effective elimination of the rounding logic on FP arithmetic units. First, we experimentally show that HUB and standard formats provide equivalent signal-to-noise ratio on DSP application implementations. We then present a detailed study of the improvement achieved when implementing FP adders and multipliers on FPGAs by using HUB numbers. In most of the cases studied, the HUB approach reduces resource use and increases the speed of these FP units while always providing statistically equivalent accuracy as that of conventional formats. However, for some specific sizes, HUB multipliers require far more resources than the corresponding conventional approach.