HPWL Formulation for Analytical Placement Using Gaussian Error Function

Abstract

Placement is a crucial stage in the physical design of VLSI(Very Large Scale Integration). Analytical placer at this stage determines optical physical locations of cells in the chip while minimizing the total half-perimeter wirelength(HPWL) of the nets. The constraints imposed while minimizing the total HPWL of nets are non-overlapping of blocks, congestion, delay etc. This paper introduces a recursive smooth wirelength model for HPWL of a net using Gaussian error function, which can be used by analytical placers. The novelty of this model lies in approximating closely the HPWL of a net than other state-of-the-art wirelength models in the literature including log-sum-exponent(LSE), weighted average(WA), CHMAX and absolute wirelength(ABSWL) models. The HPWL accuracy of the proposed model for global and detailed placements for IBM ISPD 2004 benchmark suite shows less than 1% and 0.5% absolute errors in total wirelength in average respectively.