Abstract

The combination of Moore's law and Dennard's scaling laws constituted the fundamental guidelines that provided the semiconductor industry with the foundation of a technically and economically viable roadmap until the end of the previous century. During this time, the transistor evolved from bipolar to PMOS to NMOS to CMOS. However, by the mid-1990s it was clear that fundamental physical limits of the MOS transistor were going to halt Dennard's scaling by 2005, at best. Eventually the power consumed by a single IC, under the relentless growth in the number of transistors and the continuous increase in operating frequency, pushed the IC temperature beyond reliable limits. Several memory devices operating on completely physics principles have been invented in the past 10 years and have already demonstrated that computing performance can be substantially improved by monolithically integrating several of these heterogeneous memory layers on top of logic layers powered by a combination of CMOS and new switch transistors. This phase, called 3D power scaling, will continue to support increase in transistor count at Moore's law pace well into the next decade.

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