Hot Data Detector based High-Performance NAND and PRAM Hybrid Storage

Abstract

The high-performance and low cost NAND Flash and PRAM (Phase-changed RAM) hybrid storage designs have been proposed for embedded systems. However, the system is still suffering from serious performance degradation for continuous write/read operations in the same logical address frequently due to physical constraints of NAND Flash: erase-before-program and different unit size of erase and program operation. To deal with these constraints, a hot data detector is added in the FTL (Flash Translation Layer) of the NAND flash and PRAM hybrid architecture. In this paper, a circular queue based hot data detector algorithm (CQHDD) is proposed, which mainly includes hot-area counting queue design, queue update algorithm and hot-area counting algorithm. Comparing to existing methods, the simulation results show that the read and the write performance of the suggested method improve by 14.2% and 23.7%, respectively, and the average recognition missing rate decreases by 6.3%. Index Terms - NAND flash; Phase-changed (PRAM); Hot data detection; Hybrid Storage; Flash Translation Layer