Hot carrier stress effect on the performance of 65 nm CMOS low noise amplifier

Abstract

The effects of hot carrier stress on the characteristics of NMOSFETs and low noise amplifier (LNA) in 65 nm CMOS technology are investigated. The method of determining the stress condition is explained to achieve the maximum substrate current where maximum damage is generated in NMOSFETs. The increase in threshold voltage caused by hot carriers leads to a drop in the biasing current of the transistors. These effects lead to a decrease in the transconductance and output conductance of the device. There is almost no change in the subthreshold swing, gate-source and gate-drain capacitances. In the LNA, a drop of the power gain, power consumption, figure of merit (FoM) and an increase of the noise figure have been observed after hot carrier stress. However, the hot carrier stress has no effect on the optimal width of the MOSFET in the LNA circuit.