Hot-Carrier Degradation Rate of High-Voltage Lateral Diffused Metal–Oxide–Semiconductor Field-Effect Transistors under Maximum Substrate Current Stress Conditions

Abstract

In this study, hot-carrier stresses in high-voltage (HV) lateral diffused metal-oxide-semiconductor field-effect transistors (LDMOSFETs) are applied under maximum substrate current (ISub,max) conditions with different VDS and VGS. The power index of the hot-carrier degradation rates is not always 0.5 upon stressing under different ISub,max conditions, and the HV LDMOSFETs do not exhibit the hot-carrier degradation behavior observed in low-voltage (LV) metal–oxide–semiconductor field-effect transistors (MOSFETs). In order to explain why the degradation rates under ISub,max conditions differ with different biases, two-dimensional simulators are used to elucidate the degradation mechanism in HV LDMOSFETs. It is found that under different ISub,max conditions, the highest impact ionization is located at different positions in the drift region of the device. Due to the different gate-control abilities of these regions, the current densities affected by the hot-carrier-induced interface-trapped charges are different. Thus the hot-carrier degradation rates also differ. Furthermore, due to the different depths of the impact ionization region, the amounts of initial hot-carrier-induced interface-trapped charges differ and thus the power-law pre-coefficient A also differs.