Abstract
Silicon photonics has become a commonly used paradigm for on-chip interconnects to meet the requirements of higher bandwidth in computationally intensive applications for manycore processors. Design of an optical switch is a vital aspect while constructing an optical NoC topology which influences the performance of network. We present a HoneyComb optimized reconfigurable optical switch (HCROS), a 6 × 6 non-blocking optical switch where optimized reconfiguration of optical links utilizing the states of basic 2 × 2 optical switching elements (OSE) was achieved while keeping the input-output (I/O) interconnection intact. The proposed 6-port HCROS architecture was further optimized to reduce the number of OSEs to minimize overall power consumption. We proposed a generic algorithm to find the optimal switching combination of OSEs for a particular I/O link to minimize the insertion loss and power consumption. In comparison to other non-blocking architectures, a maximum of 66% reduction in OSEs was observed for the optimized HCROS, which consumes only 12 OSEs. Simulations were performed for all 720 I/O links in different configurations to evaluate the power consumption and insertion loss. We observed up to 92% power savings in the case of optimized HCROS as compared to un-optimized HCROS, and a 79% minimization in insertion loss was also reported as a result of optimization.
Highlights
With the advent of the manycore era, hundreds to thousands of cores are expected to be fabricated on a single die for various applications, including the internet of things (IoT), machine learning, and high performance computing where higher bandwidth requirements are highly anticipated in the near future [1,2,3]
Our analysis shows that optimized HoneyComb optimized reconfigurable optical switch (HCROS) with optimized reconfiguration with 12 optical switching elements (OSE) shows significant improvements in overall power consumption and insertion loss in comparison to un-optimized HCROS
We proposed an optimized reconfigurable architecture of a 6 × 6 optical switch called the HoneyComb optimized reconfigurable optical switch (HCROS) in different configurations
Summary
With the advent of the manycore era, hundreds to thousands of cores are expected to be fabricated on a single die for various applications, including the internet of things (IoT), machine learning, and high performance computing where higher bandwidth requirements are highly anticipated in the near future [1,2,3]. Designing optical switch architecture with an optimum number of OSE can minimize overall insertion loss and power consumption in the network topology [21]. We present a generic algorithm to find the optimal switching combination with the minimal number of OSE in an active, i.e., drop/bar state, which is used to complete the process of optimized reconfiguration to minimize the IL and power consumption. We identify a particular switching combination, where all OSEs are found in an inactive state that leads to minimum power consumption through optimized reconfiguration of the proposed HCROS. (optimal state) to reconfigure OSEs in HCROS to reduce power consumption and minimize insertion loss ensuring the input to output interconnections are terms: unaffected.
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