Abstract

Hole trapping characteristics in thin (10 nm) thermally grown silicon dioxide (SiO2) in flash memory device with n-type floating polycrystalline silicon (poly-Si) gate have been theoretically investigated under Fowler–Nordheim (FN) constant current and voltage stress. Theoretical results of gate voltage shift ΔVG or ΔVFN due to trapped holes show good agreement with experimental data of Park and Schroder [IEEE Trans. Electron Devices ED-45, 1361 (1998)] during constant current injection. Our theoretical analysis based on hole injection from the poly-Si gate (anode) at injected electron fluence Qinj as low as 0.01 C/cm2 address that constant voltage stress degrades the gate oxide quality faster than constant current stress due to enhanced charge trapping and trap creation rate under constant voltage stress.

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