Hole trapping and interface state generation during bias-temperature stress of SiO2 layers

Abstract

Avalanche hole injection measurements on unstressed metal-oxide-semiconductor capacitors and those having undergone bias-temperature stress (BTS) are compared. The results show that the negative midgap voltage shift (ΔVmg) occurring during negative BTS is due to filling of intrinsic hole traps. Conversely, positive BTS removes any previously trapped holes from the oxide. No evidence was found for hole trap generation at either stress polarity. Interface state generation across the band gap accompanies hole trapping during negative BTS and a characteristic peak is generated in the interface trap distribution at ∼ 0.2 eV above midgap on neutralization or detrapping of these holes during positive BTS.