Hole trap level generation in silicon during rapid thermal annealing: Influence of substrate type and process conditions

Abstract

Hole trap level generation in boron-doped silicon by rapid thermal annealing between 900 and 1100 °C has been studied using deep level transient spectroscopy, with emphasis on the effects of substrate type and process parameters. A dominant hole trap level at Ev+0.30 eV and two accompanying hole trap levels at Ev+0.22 eV and Ev+0.40 eV in lower concentrations have been systematically detected in Czochralski, float zone, and epitaxial substrates, in a less than 5-μm-thick surface layer. The defect state concentrations were observed to increase monotonically with both the annealing temperature and the cooling rate. Higher concentrations of hole trap levels were measured in the Czochralski and epitaxial substrates than in the float zone substrate. Finally, both a silicidation and an oxidation reaction during the high-temperature plateau totally inhibited the formation of defect states. We suggest that the defect centers responsible for the observed hole trap levels could be formed during the high-temperature plateau with the participation of dissolved as-grown impurities and metal contaminants diffused from the wafer surface.