HLshield: a reliability enhancement framework for high-level synthesis

Abstract

High-Level Synthesis (HLS) is more and more becoming an important part of the digital logic design flow. Rapid development of hardware offloading designs implemented in FPGA accelerators or in the programmable logic area of modern SoC FPGAs is facilitated by the ability of today’s HLS tools to generate logic from generic programming languages such as C and C++. When such accelerators are used in applications requiring high reliability, such as safety-critical systems, the designer has to consider the possibility of soft errors occurring during run time. In this paper, the HLShield framework is proposed that aims at integrating approaches from previous work and novel techniques into the HLS process to eliminate the need to add fault tolerance functionality to the generated Hardware Description Language (HDL) code by hand. The proposed framework provides means for profiling the reliability of the original high-level source code. It allows to direct the generation of reliability-enhanced hardware descriptions by specifying the desired protection methods using source code annotations. Means for evaluating the reliability of the selected solution are also included in the framework. A proof of concept implementation for the proposed framework is presented which is able to protect registers and memories corresponding to selected variables in the original high-level source code with errorcorrecting codes. This process is supported by a profiling tool that suggests especially critical variables. The achieved reliability improvements were evaluated using fault injection experiments carried out on multiple protection levels of three use case designs. Evaluations showed that significant gains in reliability can be made when using the presented profiling approach to protect storage elements in the generated hardware.