Abstract
ABSTRACTThe process-induced stress in interconnects within integrated circuits (IC) has a direct influence on the mean time to failure of the devices. Since measurement of stress in individual metallised lines is not possible by existing techniques, another approach has been adopted where a test structure is generated during fabrication based on a micro-rotating cantilever sensor. To support the design, finite element modeling (FEM) has been performed. By comparing the rotation predicted by FEM simulations and that observed experimentally, a clear discrepancy is observed which is critically dependent on the details of the sensor design, the pattern transfer of the lithographic process and on the dry etching processing.
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