High-Voltage Technology Based on Thin Layer SOI for Driving Plasma Display Panels

Abstract

A novel high-voltage thin layer SOI technology based on 1-mum-thick silicon layer and 2-mum-thick buried oxide layer for driving color plasma display panels (PDP) has been developed. High-voltage pLDMOS with thick gate oxide, high- voltage nLDMOS, and low-voltage CMOS are compatible with LOCOS isolation. The proposed technology includes two aspects: first, an implantation after field oxide (IFO) technology is developed for achieving shallow junction depth of p-field region to avoid punch-through breakdown induced by back-gate (BG) effect of pLDMOS; second, conforming technology of isolation and oxidation is adopted for forming thick gate oxide of high-voltage pLDMOS, field oxide isolation of low-voltage CMOS, and full dielectric isolation between high-voltage and low-voltage CMOS simultaneously without additional mask and process. Compared with conventional technology of junction or trench isolation, the new high-voltage thin layer SOI technology achieves better process compatibility with lower process complexity and lower parasitic capacitance. A PDP data driver IC using the developed technology shows that the rise and fall times of the output stages are about 230 ns and 160 ns respectively under the supply voltage of 80 V and load capacitance of 50 pF.