Abstract
We are developing a system using a high-T/sub c/ superconductor (HTS) sampler for measuring a 40-Gbps digital signal waveform, which will be used in next generation ultra-high-speed communications. To measure a 40-Gbps digital signal, the sampler bandwidth needs to be more than 120 GHz. The HTS sampler has the potential to achieve this bandwidth. As a first step in developing this system, we have developed a prototype whose target bandwidth is 40 GHz. In the prototype system, the sampler chip is cooled down to 35 K by a single-stage Stirling cryocooler, and the digital signal is transmitted to the sampler chip via a 40-GHz bandwidth assembly line. This system is the first to integrate an HTS device, a cryocooler, and a high-frequency assemble line. A 5.9-Gbps digital waveform was reconstituted by the prototype system with the correct period.
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