High-Temperature Annealing Effects on Atomically Thin Tungsten Diselenide Field-Effect Transistor

Abstract

Two-dimensional (2D) material-based devices are expected to operate under high temperatures induced by Joule heating and environmental conditions when integrated into compact integrated circuits for practical applications. However, the behavior of these materials at high operating temperatures is obscure as most studies emphasize only room temperature or low-temperature operation. Here, the high-temperature electrical response of the tungsten diselenide (WSe2) field-effect transistor was studied. It is revealed that 350 K is the optimal annealing temperature for the WSe2 transistor, and annealing at this temperature improves on-current, field-effect mobility and on/off ratio around three times. Annealing beyond this temperature (360 K to 670 K) adversely affects the device performance attributed to the partial oxidation of WSe2 at higher temperatures. An increase in hysteresis also confirms the formation of new traps as the device is annealed beyond 350 K. These findings explicate the thermal stability of WSe2 and can help design 2D materials-based durable devices for high-temperature practical applications.