High-speed VLSI designs for Lempel-Ziv-based data compression

Abstract

A class of hardware algorithms for implementing the Lempel-Ziv-based data compression technique is described. The Lempel-Ziv-based compression method is a powerful technique for lossless data compression that gives high compression efficiency for text as well as image data. The proposed hardware algorithms exploit the principles of pipelining and parallelism in order to obtain high speed and throughput. A prototype CMOS VLSI chip was designed and fabricated using 2- mu m CMOS technology implementing a systolic array of nine processors. The chip gives a compression rate of 13.3 MB/s operating at 40 MHz. Two hardware algorithms for the decompression process are also described. The data compression hardware can be integrated into real-time systems so that data can be compressed and decompressed on-the-fly. >