High-speed Sparse Ising Model on FPGA

Abstract

To implement the Ising model on hardware and create things able to process optimization problems for the future Internet of Things (IoT), a method is proposed for speeding up an Ising model, which is equivalent to being able to reduce power. By implementing a 6×6 spin Ising model in a 16 nm complementary metal-oxide-semiconductor field-programmable gate array (CMOS FPGA), we found that the optimal solutions can be given for the traveling salesman problem (TSP), which is the typical combinatorial optimization problem, and the support vector machine (SVM), which is a general optimization problem. By implementing parallel updates, higher processing speed is achieved. Furthermore, the Ising model in which the interactions are reduced on the basis of the sparsity is more than nine times faster than the fully connected Ising model according to measurement with an FPGA. As a result, an Ising model on an FPGA is demonstrated with high speed, equivalent to being able to reduce power for IoT applications.