High-Speed Parallel Decodable Nonbinary Single-Error Correcting (SEC) Codes

Abstract

This paper presents a novel construction scheme for nonbinary single-error correcting (SEC) codes that yields high-speed parallel decoding. The proposed scheme utilizes two methods, namely, Improved and Reordered; these methods can be also combined. Both of these methods reduce the number of 1's in the parity-check matrix (H-matrix) by reducing the 1's in every row vector. This results in a reduction in the gate depth in the syndrome generator, thus achieving a shorter delay time for parallel decoding. In the proposed Improved method, for a single $b$ -bit byte (i.e., $\mbox{2}^{b}$ -ary symbol) error correcting code, the submatrix of the H-matrix corresponding to every $b$ -bit byte is multiplied with a regular matrix. The so-called improved submatrix is generated using a heuristic (greedy) algorithm. The proposed Reordered method selects the correct $b$ -bit bytes for deletion when shortening is performed. Simulation results show that the proposed scheme accomplishes a faster parallel decoding time than existing schemes. Furthermore, the proposed scheme is applicable to any class of linear SEC codes, whereas existing schemes are applicable only to specific codes. Extensive simulation results are provided to substantiate the viability of the proposed codes for faster parallel decoding (albeit incurring for most cases in modest increases of area and power dissipation due to additional circuitry).