Abstract
KASUMI block cipher is used for the security part of many synchronous wireless standards. In this paper two architectures and efficient implementations of the 64-bit KASUMI block cipher are presented. In the first one, the pipeline technique (inner-round and outer-round pipeline) is used and throughput value equal to 3584 Mbps at 56 MHz is achieved. The second one uses feedback logic and reaches a throughput value equal to 432 Mbps at 54 MHz. The designs were coded using VHDL language and for the hardware implementations, a FPGA device was used. A detailed analysis, in terms of performance, and covered area is shown. The proposed implementations outperform any previous published KASUMI implementations in terms of performance.
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