High-speed hardware implementation of a serial-in parallel-out finite field multiplier using reordered normal basis

Abstract

A high-speed VLSI implementation of a 233-bit serial-in parallel-out finite field multiplier is presented. The proposed design performs multiplication using a reordered normal basis; a permutation of a type II optimal normal basis. The multiplier was realised in a 0.18-?m CMOS technology using multiples of a domino logic block. The multiplier was simulated, and functioned correctly up to a clock rate of 1.587 ?GHz, achieving greater performance while occupying less area compared to similar designs. The presented design methodology can also be used for other finite field multipliers possessing regular architectures. This multiplier?s size of 233 bits is currently recommended by the National Institute of Standards and Technology (NIST) in their elliptic curve digital signature standard (ECDSS), and is used in practice for binary field multiplication in Elliptic Curve Cryptography (ECC).