Abstract
A high-speed column driver IC with an area-efficient high-slew-rate buffer amplifier is proposed for use in a large-sized, high-resolution TFT-LCD panel application. In the proposed architecture, explicit isolation switches have been embedded into the buffer amplifier resulting in a fast settling response. The amplifier also has a structure that adjusts the tail current of the input stage using a very compact adaptive biasing. The proposed column driver IC, having the proposed buffer amplifier for driving a 55-inch 4K ultra-high-definition (UHD) TV panel, was fabricated in a 0.18-μm 1.8-V low-voltage, 1.2-μm 9-V medium-voltage, and 1.6-μm 18-V high-voltage CMOS process. The performance evaluation results indicated that 90% and 99.9% falling settling times were improved from 1.947 µs to 0.710 µs (63.5% improvement) and 4.131 µs to 2.406 µs (41.7% improvement), respectively. They also indicated that the layout size of the proposed buffer amplifier was reduced from 5580 μm2 to 4402 μm2 (21.1% reduction).
Highlights
Large-sized, high-resolution, flat-panel display (FPD) monitors and TVs require lowpower, small-area, high-slew-rate amplifiers as column drivers [1,2,3,4,5,6,7,8,9,10]
A column driver for a large FPD typically requires receiver comparators, data registers, and shift registers, which are composed of low-voltage transistors, gamma reference voltages and digital-toanalog converters (DACs), which are composed of middle-voltage transistors, level shifters and output buffers with output-polarity switches, which are composed of high-voltage transistors [1,2,3,4,5,6,7,8,9,10,11,12,13,14]
A column driver with a high-speed driving scheme and an area-efficient high-slewrate buffer amplifier for FPD applications is proposed in this paper
Summary
Large-sized, high-resolution, flat-panel display (FPD) monitors and TVs require lowpower, small-area, high-slew-rate amplifiers as column (data or source) drivers [1,2,3,4,5,6,7,8,9,10]. A high-slew-rate low-power buffer amplifier with small active area is still required for use in FPD column driver ICs. In this paper, to address the issues mentioned above, an adaptively biased high-slewrate output buffer amplifier and a high-speed column-line driving method are proposed. We present a novel buffer amplifier with embedded isolation switches and a very compact adaptive biasing circuit to improve the settling time and reduce overheads in terms of chip area and power consumption. In the proposed output buffer amplifier, the voltage levels of Pup and Pdn driving output transistors MPD1 and MND1 and auxiliary current sources MPT1A and MNT1A, respectively, are adjusted for a push–pull operation of the driver in conjunction with the capacitive load at the output. The compact design of the proposed buffer amplifier allows our driving scheme to be more area- and energy-efficient with substantially improved settling performance
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