High-Speed Architecture Design of Tomlinson–Harashima Precoders

Abstract

Like decision feedback equalizers (DFEs), Tomlinson-Harashima precoders (TH precoders) contain nonlinear feedback loops, which limit their use for high-speed applications. Unlike in DFEs where the output levels of the nonlinear devices are finite, in TH precoders, theoretically, the output levels of the modulo devices are infinite. Thus, it is difficult to apply look-ahead and pre-computation techniques to pipeline TH precoders, which were successfully applied to pipeline infinite-impulse response (IIR) filters and DFEs in the past. In this paper, three approaches are proposed to design high-speed TH precoders. In the first approach, the traditional block processing technique for DFEs is generalized to the design of high-speed TH precoders. In the second approach, based on the equivalent form of a TH precoder where the precoder can be viewed as an IIR filter with an input equal to the sum of the original input to the TH precoder and a finite-level compensation signal, two high-speed pipelined designs are developed. In the third approach, parallel processing techniques for fast IIR filters are generalized to the design of parallel TH precoders.