High-speed and low-power interconnect technology for sub-quarter-micron ASIC's

Abstract

The optimum interconnect structure for and low-power sub-quarter-micron Application Specified Integrated Circuits (ASIC's) is investigated. High-speed and low-power scaling rules for the interconnect structures are extracted statistically from the wiring data in actual ASIC's. Adopting the scaling for a 0.25-/spl mu/m ASIC enables us to reduce the gate delay by 23% and the gate power by 31% compared to conventional (horizontal only) scaling rule. A low-dielectric-constant interlayer insulator further reduces both the gate delay and power by reducing wiring capacitance. A 0.25-/spl mu/m interconnect structure was fabricated by adopting the high-speed and low-power interconnect scaling rule and using organic spin-on-glass (SOG) as a low-dielectric-constant interlayer insulator. According to equivalent-circuit calculation using the measured interconnect parameters, the gate delay was reduced by 39% and the gate power was reduced by 47% compared to a conventional interconnect structure.