High-Power Generation for mm-Wave 5G Power Amplifiers in Deep Submicrometer Planar and FinFET Bulk CMOS

Abstract

A review is presented of the key techniques for high-power, high-efficiency millimeter-Wave (mm-Wave) 5G power amplifier (PA) design in deep submicrometer planar and FinFET bulk CMOS processes. The work utilizes a distributed unit cell-based layout technique for neutralized differential pairs and stacking transistors in bulk CMOS. This article also proposes a prediction of saturated output power (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> ) and its corresponding maximized power-added efficiency (PAE) at 39 GHz for three candidate power combined architectures of three-stage PAs with two supporting prototype PAs fabricated in 16-nm FinFET and 28-nm planar bulk CMOS processes. The single-stage two-stack 16-nm FinFET PA generates a P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> of 18.3 dBm from a 1.8-V supply at 39 GHz with a drain efficiency (DE) of 35.5%. The three-stage 28-nm PA incorporates a two-stack output stage with a balanced and compact 4-to-1 series-parallel combiner and achieves a P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> of 26 dBm using a 2.2-V supply, PAE of 26.6%, and high average power measurements with single-carrier and 5G new radio orthogonal frequency-division multiplexing modulations with competitive efficiencies. Long-term reliability measurements are performed using aging acceleration techniques to demonstrate the robustness of both prototypes. The competitive power and efficiency results, supported with reliability measurements, show that bulk CMOS can achieve performance comparable to SOI CMOS for generating high power at mm-Wave frequencies.