High-performance VLSI architecture of adaptive decision feedback equalizer based on predictive parallel branch slicer (PPBS) scheme

Abstract

Among existing works of high-speed pipelined adaptive decision feedback equalizer (ADFE), the pipelined ADFE using relaxed look-ahead technique results in a substantial hardware saving than the parallel processing or Look-ahead approaches. However, it suffers from both the signal-to-noise ratio (SNR) degradation and slow convergence rate. In this paper, we employ the predictive parallel branch slicer (PPBS) to eliminate the dependencies of the present and past decisions so as to reduce the iteration bound of decision feedback loop of the ADFE. By adding negligible hardware complexity overheads, the proposed architecture can help to improve the output mean-square error (MSE) of the ADFE compared with the Relaxed Look-ahead ADFE architecture. Moreover, we show the superior performance of the proposed pipelined ADFE by using theoretical derivations and computer simulation results. A VLSI design example using Avant! 0.35-/spl mu/m CMOS standard cell library is also illustrated. From the post-layout simulation results, we can see that the PPBS scheme requires only 38.4% gate count overhead, but it can help to reduce the critical path from 7.06 to 4.69 ns so as to meet very high-speed data transmission systems.