High-performance STT-MRAM Logic-in-Memory Scheme Utilizing Data Read Features

Abstract

In the Big Data era, enormous amounts of data processing have caused an intolerable 'memory wall' challenge for traditional Von Neumann architectures. Therefore, more advanced Logic-in-memory (LiM) computing architectures are proposed with integrated computing and memory units that reduce data migration. The emerging non-volatile memory STT-MRAM, with its fast access speed, near-zero leakage power consumption and high density is one of the most competitive carriers for LiM architectures. This work introduces the principle of LiM and proposes four basic logic operations (XNOR, XOR, AND and OR) based on STT-MRAM. Incorporating the reading characteristics of STT-MRAM and slight modifications to the peripheral circuitry, these operations achieve significant optimisation in terms of latency and energy consumption. From the experimental results, the proposed scheme can reduce the latency of XOR, AND and OR operations at least by 99.3%, 82.2% and 80.2% compared with the existing design. Also, 500 Monte Carlo samples prove the feasibility and robustness of the proposed scheme.