High-performance NoC Interface with interrupt batching for Micronmesh MPSoC prototype platform on FPGA

Abstract

This paper presents a new NoC Interface (NI) targeted for improving the performance of the Micronmesh Multiprocessor System-on-Chip (MPSoC). The previous version of the NI called Micronswitch Interface (MSI) can zero-copy messages as it sends and receives them. It offloads also some functionalities of the communication protocol from software (SW) to hardware (HW), but interrupt processing produces extra SW overhead and reduces the performance. For this reason, an improved version of the MSI called MSI-with-Queues (MSIQ) was designed with a new queue mechanism in order to reduce the frequency of interrupts and the SW overhead. Owing to the new queue mechanism of the MSIQ it is possible to batch and service multiple interrupt service requests by every execution of the Interrupt Service Routine (ISR). Additionally, the new MSIQ HW is able to send and receive messages while the processor is running the ISR. The performance of the MSIQ is also analyzed in this paper. The results show that the queue mechanism improves the performance with moderate hardware costs.