High‐performance low‐power approximate Wallace tree multiplier

Abstract

SummaryMultipliers are considered critical functional units in many systems like Digital Signal Processing (DSP), machine learning, and so on. The overall performance of such systems are dependent on the efficiency of multipliers. However, multipliers are slow and power inefficient components due to their complex circuits, so we aim to reduce their power consumption by relaxing their accuracy requirements and at the same time enhancing their speed. In this paper, we present a fast and a power‐aware multiplier that targets error‐resilient systems. This is achieved by using our proposed approximation algorithm, a hybrid Wallace tree technique for reducing power consumption, and a hybrid ripple‐carry adder for reducing latency. The proposed approximation algorithm is implemented using both a modified bit‐width aware and carry‐in prediction technique, while the proposed hybrid Wallace tree is implemented using high order counters. These proposed algorithms are implemented using HDL language, synthesized, and simulated using Quartus and Modelsim tools. For a 16‐bit multiplier, a mean accuracy of 98.35% to 99.95% was achieved with a 45.77% reduction in power, a 21.48% drop in latency, and a 34.95% reduction in area. In addition, our design performs even better for larger size multipliers (32‐bit multiplier) where a 61.24% reduction in power was achieved, with an 8.74% drop in latency and a 35.24% reduction in area with almost no loss in accuracy.