High-Performance GraphBLAS Backend Prototype for NEC SX-Aurora TSUBASA

Abstract

Developing efficient graph algorithm implementations is a significant important problem of modern computer science since graphs are frequently used in various real-world applications. Graph algorithms typically belong to the data-intensive class, and thus using architectures with high-bandwidth memory potentially allows to solve many graph problems signif-icantly faster than modern multicore CPUs. Among other su-percomputer architectures, SX-Aurora TSUBASA vector engines are equipped with high-bandwidth memory, and thus, potentially allow to accelerate various graph applications. However, very few existing graph processing frameworks can efficiently utilize SX-Aurora hardware capabilities. GraphBLAS standard proposes a convenient way to develop graph algorithms in terms of linear algebra and allows its users not todeeply understand vector architectures hardware features. This paper describes a world-first attempt to implement an optimized prototype of the GraphBLAS backend for SX-Aurora TSUBASA. Our backend prototype can achieve performance, comparable to the existing Vector Graph Library (VGL) based implementations for SX-Aurora TSUBASA, and also outperform the existing GraphBLAS backends for NVIDIA GPUs. We also discuss the roadmap and challenges for creating the full GraphBLAS implementation for SX-Aurora TSUBASA vector engines.