Abstract
Monolayer molybdenum disulfide (MoS2) possesses a desirable direct bandgap with moderate carrier mobility, whereas graphene (Gr) exhibits a zero bandgap and excellent carrier mobility. Numerous approaches have been suggested for concomitantly realizing high on/off current ratio and high carrier mobility in field-effect transistors, but little is known to date about the effect of two-dimensional layered materials. Herein, we propose a Gr/MoS2 heterojunction platform, i.e., junction field-effect transistor (JFET), that enhances the carrier mobility by a factor of ~ 10 (~ 100 cm2 V−1 s−1) compared to that of monolayer MoS2, while retaining a high on/off current ratio of ~ 108 at room temperature. The Fermi level of Gr can be tuned by the wide back-gate bias (VBG) to modulate the effective Schottky barrier height (SBH) at the Gr/MoS2 heterointerface from 528 meV (n-MoS2/p-Gr) to 116 meV (n-MoS2/n-Gr), consequently enhancing the carrier mobility. The double humps in the transconductance derivative profile clearly reveal the carrier transport mechanism of Gr/MoS2, where the barrier height is controlled by electrostatic doping.
Highlights
Monolayer molybdenum disulfide (MoS2) possesses a desirable direct bandgap with moderate carrier mobility, whereas graphene (Gr) exhibits a zero bandgap and excellent carrier mobility
We propose an ideal device platform based on a junction field-effect transistor (JFET) architecture featuring a Gr/MoS2 heterointerface, where the carrier mobility of M oS2 is enhanced by a factor of 10, while maintaining a high on/off current ratio of up to 1 08 at room temperature
Monolayer MoS2 was intentionally stacked on top of a monolayer Gr strip that was grown by chemical vapor deposited (CVD)
Summary
Monolayer molybdenum disulfide (MoS2) possesses a desirable direct bandgap with moderate carrier mobility, whereas graphene (Gr) exhibits a zero bandgap and excellent carrier mobility. We propose a Gr/MoS2 heterojunction platform, i.e., junction field-effect transistor (JFET), that enhances the carrier mobility by a factor of ~ 10 (~ 100 cm[2] V−1 s−1) compared to that of monolayer MoS2, while retaining a high on/off current ratio of ~ 108 at room temperature. Despite lowering the Schottky barrier height and improving the carrier injection of multilayer MoS2 significantly, the choice of contact metals for the monolayer in this approach is very limited due to Fermi level pinning depending on the surface states or defect sites of the metal/MoS2 interface. We propose an ideal device platform based on a junction field-effect transistor (JFET) architecture featuring a Gr/MoS2 heterointerface, where the carrier mobility of M oS2 is enhanced by a factor of 10, while maintaining a high on/off current ratio of up to 1 08 at room temperature. The low SBH regime at n-Gr/n-MoS2 provides an additional Gr conduction path for M oS2, leading to μFE ~ 100 cm[2] V−1 s−1, whereas the high SBH regime at p-Gr/n-MoS2 blocks the contribution of Gr to M oS2, leading to μFE ~ 10 cm[2] V−1 s−1, similar to that of the pure M oS2-based device
Sign-in/Register to view highlights & summary Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
