Highly scalable flash memory embedded into high-performance CMOS for the 90nm node and beyond

Abstract

A flash memory cell with 90nm ground-rules has been embedded in a high performance (HP) CMOS logic process. A novel deep trench isolation (DTi) process module enables an isolated pwell (IPW) bias scheme, leading to flash with uniform channel program/erase (UCPE) by Fowler-Nordheim (FN) tunneling without GIDL, a key feature for low-power (LP) electronics. IPW leads to a compact cell design and a highly scalable high-voltage (HV) periphery through the narrow intrawell and interwell isolation spaces. The memory arrays are defined by DTi of each bitline (BL) from its neighboring BL. Buried BL (BBL) is another novel process concept presented in this work that links the source contacts of each individual BL via the isolated p-well; thus effectively eliminating one metal line per BL and reducing overall cell size by about 40%. The HV bias can be further scaled with a carefully designed retrograde triple-well that enables a symmetrical gate-well bias