Highly resilient 17‐level fault‐tolerant multilevel inverter topology with reduced capacitor size

Abstract

SummaryMultilevel inverters (MLIs) have recently drawn the huge attention of industry and academia since they are becoming a viable technology for a variety of applications. However, the risk of failure of the converter increases with the increasing number of component count for applications involving heavy duty and continuous operation. In this context, an asymmetrical source configured FT‐MLI (fault tolerant‐MLI) topology is investigated and developed with less number of device count and having the ability to withstand both OC (open‐circuit) and SC (short‐circuit) switch faults on single and multiple switches. The proposed architecture maintains the same output voltage levels and power in both pre‐ and post‐fault operations. In addition, a switching method is developed to reduce the capacitors' size by minimizing the voltage ripple. Furthermore, without the need for an external circuit, the voltage across the capacitors remains balanced in both pre‐ and post‐fault operations. The simulation and experimental results are provided to demonstrate the effectiveness of the proposed asymmetrical FT‐MLI topology. Finally, a comparison of the proposed topology with the existing MLI topologies is shown to emphasize the benefits of the proposed system.