Highly efficient reconfigurable routers in Networks-on-Chip

Abstract

NoC designs are based on a compromise of latency, power dissipation or energy, usually defined at design time. However, setting all parameters at design time can cause either excessive power dissipation (originated by router underutilization), or a higher latency. The situation worsens whenever the application changes its communication pattern, i.e., a portable phone downloads a new service. The buffer's depth is an important resource to assure performance, and has a great impact on power. In this paper we propose the use of a reconfigurable router, where the buffers are dynamically allocated to increase router efficiency in a NoC, even under rather different communication loads. The reconfigurable router allows up to 52% power savings, while maintain the same performance of the homogeneous original router with roughly the same area.