Highly efficient digital quadrature transmitter with dual VDD and dynamic cell selection

Abstract

A digital quadrature dual VDD transmitter with a switched capacitor power combiner is presented. To improve the efficiency, the cell in the transmitter is dynamically selected to minimise the voltage across the capacitors, thereby minimising the discharging loss. The chip is fabricated in 28-nm CMOS process. The implemented transmitter has a peak power of 17.2 dBm with a PAE of 37.4% at 880 MHz. The average power is 7.9 dBm with a PAE of 23.6% under ACLR of −32 dBc using a 10 MHz, 16 QAM, and 6.9 dB LTE signal.