High-level TSV resource sharing and optimization for TSV based 3D IC designs

Abstract

Under the current process and layer bonding technology for the TSV (through-silicon-via) based 3D ICs, it is known that the TSV resource is one of the major sources of the function failure of the chip. Furthermore, TSV takes much larger size and pitch than the normal logic components. For this reason, a careful allocation of the TSV resource has been required in 3D IC designs, and several works have been proposed to allocate TSVs minimally or economically. This work addresses the problem of TSV allocation and optimization to overcome one of the critical limitations of the previous works, which is the unawareness or no exploitation of the possibility of TSV resource sharing, previously merely resorting to a simple binding of the data transfers to TSVs. This is because the previous 3D layer partitioners have performed TSV allocation and minimization without any link to the data transfer information accessible from the high-level synthesis flow. This work proposes two TSV resource sharing and optimization algorithms (as a post-processing of 3D layer partitioning) which make use of the life time information of the data transfers taken from the high-level synthesis. Precisely, we propose two algorithms for TSV resource sharing and optimization, which can be selectively applied depending on the sharing granularity and design complexity: word-level TSV sharing and bit-level TSV sharing. Through experiments with benchmark designs, it is confirmed that our proposed algorithms are able to reduce the number of TSVs by 10.5%~41.1% in word-level TSV sharing and 15.5% ~ 45.1% in bit-level TSV sharing at the expense of 2.0% ~ 18.1% increase of 2D wirelength compared with the results produced by the conventional layer partitioning with no TSV sharing while still meeting the timing constraint of designs.