High-level synthesis assisted, low-latency, area- and power-optimized FPGA implementation of MUSIC algorithm for direction-of-arrival estimation

Abstract

For multiple signal-processing applications, estimating the target’s speed, distance, and elevation angle by using applications running in real time and consequently, fast data rates is important. Custom hardwares, such as field programmable gate arrays (FPGAs), are often used to prototype and deploy such signal-processing algorithms. Multiple signal classification (MUSIC) is typically used for direction-of-arrival (DOA) estimation. It involves complex mathematical operations such as covariance matrix computation, eigen value decomposition, and peak value search for signal values. With a novel high-level synthesis (HLS)-based design approach that optimizes the bit widths for the eigen value decomposition logic, this study presents an area and speed-optimal implementation of MUSIC algorithm on FPGA. The final implementation involving the covariance matrix computation, eigen value decomposition, and peak search was implemented on Xilinx Zynq (XC7Z020) FPGA. Because of its optimum bit widths, area utilization was minimized and operation frequency on the target FPGA was maximized. The proposed design works in real time to estimate the DOA in less than 1.7 µs (15 % faster than reported values) and uses up to 30 % less resources on the target FPGA compared with other reported implementations.