Abstract
Modelling complex, real-time systems at a high level of abstraction is becoming increasingly important with the prevalence of embedded systems. While the Unified Modelling Language (UML) has been at the forefront of the promise of model-driven development, difficulties with their semantics have prevented FPGA implementations of exact UML executable models thus far. In this paper, we propose to adapt logic-labelled finite-state machines with a well-defined, time-triggered semantics suitable for FPGA implementation. We demonstrate the viability of our approach with an implementation of communicating, cellular automata with strict timing requirements.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have