High-level BIST synthesis for delay testing

Abstract

As delay testing using an external tester requires expensive test equipment, BIST is an alternative technique that can significantly reduce the test cost. A prime concern in using BIST is the area overhead due to the modifications of normal registers to be test registers. This paper presents a BIST TPG scheme for the detection of delay faults. This scheme produces single-input change test-pair sequence which guarantees the detection of all testable path delay faults. In order to implement the proposed BIST scheme effectively, this paper exploits high-level synthesis process, and presents a data path allocation approach, which results in a minimum area BIST solution. The proposed BIST scheme and the register assignment approach were applied to academic benchmarks.