High-Efficiency Stacked Power Amplifier IC With 23% Fractional Bandwidth for Average Power Tracking Application

Wooseok Lee,Kang-Yoon Lee,Hyungmo Koo,Youngoo Yang,Sungjae Oh,Jangsup Yoon,Hwiseob Lee,Hyunuk Kang,Keum Cheol Hwang,Jongseok Bae,Hansik Oh

doi:10.1109/access.2019.2957608

Abstract

This paper presents a two-stage stacked power amplifier integrated circuit (PAIC) for broadband and high efficiency using a 2-μm InGap/GaAs HBT process with a second-harmonic control circuit and a bias-switching circuit for an average power tracking (APT) application. For APT operation, active bias circuits with a bias switching circuit for the stacked stage were proposed. A simple L-section matching network with a second-harmonic termination circuit was adopted for broad bandwidth and high efficiency. The frequency-independent power and efficiency contours for fundamental and second-harmonic frequency band were extracted at the current-source plane of the transistor. The implemented two-stage PAIC was evaluated using a long-term evolution signal with a peak-to-average power ratio (PAPR) of 7.5 dB and a signal bandwidth of 10 MHz. From 1.55 to 1.95 GHz, the power amplifier exhibited average output power ranging from 27.4 to 28.5 dBm, a power gain of more than 28.6 dB, and a power-added efficiency (PAE) of 36.5 to 41.2% at an ACLR of -30 dBc. At an average output power back-off of 5 dB, the PAE improved to 29.5% with APT using an external buck-boost dc-dc converter, while it was 18.7% without APT.

Highlights

The power amplifiers (PAs) for wireless communication systems require high efficiency, high linearity, and broadband capacity
To apply average power tracking (APT) to improve the efficiency at the average power back-off conditions, we proposed new active bias circuits with a bias switching circuit for the stacked stage
To extract frequencyindependent power and efficiency contours for both fundamental and second harmonics at the internal plane of the transistor, we modeled the parasitic output network of the transistor using a capacitor and an inductor in series and embedded it to the load-pull contours

Summary

INTRODUCTION

The power amplifiers (PAs) for wireless communication systems require high efficiency, high linearity, and broadband capacity. Because of the shunt capacitor for second harmonic control, the fundamental impedance matching network had a higher quality factor (Q), which limited the bandwidth.In [18], a broadband PA using a stacked and differential structure with a fractional bandwidth (FBW) of 17.3% was reported. We adopted a stacked structure and a simple L-section based fundamental matching network with a second-harmonic termination circuit and a low ITR for broad bandwidth and high efficiency. To extract frequencyindependent power and efficiency contours for both fundamental and second harmonics at the internal plane of the transistor, we modeled the parasitic output network of the transistor using a capacitor and an inductor in series and embedded it to the load-pull contours. In addition to lower ITR, we could obtain more output power using the stacked PA with a higher supply voltage than that of the common emitter structure. Using the optimum load impedance (ZL ) of 12+j13.8 at the center frequency of 1.75 GHz, the optimum resistance at the internal plane was 28 from (1) in our design

POWER AND EFFICIENCY CONTOURS WITH A SECOND-HARMONIC CONTROL

OUTPUT MATCHING NETWORK WITH AN OPTIMIZED SHUNT INDUCTOR

Findings

CONCLUSION