High-Efficiency Heterojunction with Intrinsic Thin-Layer Solar Cells: A Review

Abstract

Heterojunction with intrinsic thin layer (HIT) solar cell has attracted attention of photovoltaic research community due to its low process temperature, as compared to crystalline silicon (c-Si) solar cell and relatively high efficiency (η). In this solar cell structure, thin intrinsic amorphous silicon layers are used as surface passivator, which also acts as buffer layer at the top as well as bottom surfaces of n-type crystalline silicon (c-Si) wafer. A thin p-type a-Si top layer acts as an emitter while highly doped n-type bottom layer is used as a back surface field. There have been suggestions that the device performance comes with significant tunnelling transport of the charge carriers across junction barriers, whereas other investigation suggests that the diffusion of the carriers may be adequate. Various experimental as well as theoretical investigations were carried out to characterize and improve performance of HIT solar cell. For example, it was reported that a thicker p-type emitter (up to 40nm) shows higher open circuit voltage, although short circuit current density (Jsc) and cell efficiency decreases. Recent investigation showed that when the p-type and i-type layer thickness increased (within 4 nm) the open circuit voltage (Voc) as well as the efficiency improves. Using thinner c-Si absorbed is another interesting aspect in which a light trapping scheme can be combined to achieve a better performance characteristics. There has been several theoretical as well as experimental investigations on the use of various types of emitter layer and intrinsic layer of the cell, and their role on the Jsc, Voc, η and fill factor (FF). Investigations of HIT solar cell on p-type c-Si wafers have also been carried out. In this article we will present a brief review on some of the important aspects of the HIT solar cell.