High-Density Three-Dimensional Stacked nand Flash With Common Gate Structure and Shield Layer

Abstract

A new 3-D stacked NAND Flash memory is proposed to achieve high density by using common gate structure and shield layer. By adopting trench structure instead of through-hole structure, threshold voltage (Vth) variation in cells of a cell string can be reduced, and the number of stacked control-gate (CG) electrodes in a gate stack can be increased as a result. In the trench between adjacent CG stacks, gate O/N/O stack, poly-Si bodies, backside oxide, and shield layer are formed. To investigate the key characteristics of the memory, we fabricated proposed 3-D stacked NAND Flash memory cell strings which have three layers of vertically stacked CGs. Vth could be controlled by applying a bias to the shield layer. We also showed reasonable cycling and retention characteristics of a cell in a string and good pass-gate properties of the cell in the bottom of the trench.