High-Density Single-Poly Electrically Erasable Programmable Logic Device for Embedded Nonvolatile Memory Applications

Abstract

A novel electrically erasable programmable logic device (EEPLD) memory cell with new program and erase operations fabricated by a standard complementary metal–oxide–semiconductor (CMOS) logic process is presented. The cell which consists of two metal–oxide–semiconductor field effect transistor (MOSFET) transistors in series is programmed by select-gate-controlled drain avalanche hot hole injection and erased by channel hot electron injection. The cell exhibits good programming and erasing characteristics along with endurance up to 105 cycles, and 1000 h of data retention at 150°C. A new self-converged programming scheme is investigated for multilevel or analog storage. Without a P-well or an N-well serving as a coupling gate, the novel cell provides the smallest area size per bit reported for a single-poly nonvolatile memory. With its small cell size and full compatibility with the standard CMOS logic process, the novel EEPLD can be easily adopted in highly integrated VLSI systems.