Abstract
An analogue CMOS buffer configuration, which eliminates the tradeoff between high bandwidth and very low input capacitance, has been designed and simulated in a standard 2 μm process. The circuit shows a total input capacitance less than 50 fF up to 12 MHz and less than 110 fF overall with a 3 dB bandwidth of 20 MHz when driving a 15 pF and 100 kω load. The very small input capacitance and high bandwidth make the circuit very suitable for testing internal sensitive nodes in CMOS analog or mixed-mode circuits.
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