Abstract
We report high yield sub-0.1μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> SRAM cells using high-k/metal gate FinFET devices. Key features are (1) novel fin patterning strategy, (2) double gate patterning (3) new SRAM cell layout and (4) EUV lithography and robust etch/fill/CMP for contact/metal 1.0.099μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> FinFET 6T-SRAM cells show good yield. And smaller cells (0.089μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) are functional. Further yield improvement is possible by junction optimization using extension less junction approach and further cell layout optimization.
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