Abstract

We report the impact of high work-function (/spl Phi//sub M/) metal gate and high-K dielectrics on memory properties of NAND type charge trap flash (CTF) memory devices. In this article, theoretical and experimental studies show that high /spl Phi//sub M/ gate and high permittivity (high-K) dielectrics play a key role in eliminating electron back tunneling (EBT) through the blocking dielectric during the erase operation. Techniques to improve erase efficiency of CTF memory devices with a fixed metal gate by employing various chemicals and structures are introduced and those mechanisms are discussed.

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