High voltage protection in active matrix flat-panel imagers

Abstract

Various direct and indirect active matrix flat-panel imagers (AMFPI) are being investigated for x-ray imaging. In both direct AMFPI and indirect AMFPI with avalanche gain, a bias potential up to several thousand volts is required to operate the photoconductor. Under the condition of a large amount of radiation exposure between subsequent readout, a potential >80 V could appear across the amorphous silicon (a-Si) thin film transistor (TFT) and cause permanent damage. The purpose of this paper is to investigate a simple pixel design for high voltage protection. The pixel electrode acts as an additional gate for the top channel of an a-Si TFT to drain excess image charge from the pixel electrode until an equilibrium is reached where the TFT channel current equals the detector signal current at a predetermined safe maximum value V Pmax for the pixel potential. This TFT structure without additional protective device simplifies the TFT array design and improves yield. However special care is required to understand the characteristics of both the top and the bottom gates to ensure sufficient detector dynamic range as well as reliable high voltage protection. A physical model for dual-gate a-Si TFTs was developed and device parameters were determined by fitting the model to measured characteristics from a dual-gate TFT array. Our results showed that compared to the bottom (normal) gate, the protective gate has a shallower transfer characteristics (i.e. channel current as a function of gate voltage) due to a higher density of states in the top interface. Nevertheless it provides adequate protection of the TFT with V Pmax of ~40 V for typical radiographic exposures.