High voltage NPN-bipolar transistor using P/sup +/-buried layer in BiCMOS process

Jun-Lin Tsai Jun-Lin Tsai,Jei-Feng Huang Jei-Feng Huang,Ruey-Hsin Liou Ruey-Hsin Liou,Shun-Liang Hsu Shun-Liang Hsu,Jeng Gong Jeng Gong,Shih-Hui Chen Shih-Hui Chen

doi:10.1109/iedm.1999.823876

High voltage NPN-bipolar transistor using P/sup +/-buried layer in BiCMOS process

Jun-Lin Tsai Jun-Lin Tsai, Jei-Feng Huang Jei-Feng Huang + Show 4 more

https://doi.org/10.1109/iedm.1999.823876

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Publication Date: Dec 5, 1999

Affiliation: Taiwan Semiconductor Manufacturing Company (Taiwan), National Tsing Hua University

#High Voltage #High Early Voltage + Show 8 more

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Abstract

An easy to implement high voltage NPN transistor is integrated in a low voltage (LV) thin (4.5 /spl mu/m) epi-layer BiCMOS process. In this high voltage (HV) bipolar transistor, the conventional N/sup +/-buried layer of the collector is replaced with a P/sup +/-buried layer. The breakdown voltage is higher than 90 V. High current gain (>140), high Early voltage (>500 V), and high frequency response (>1.3 GHz) are also obtained.

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