High Trigger Current NPN Transistor With Excellent Double-Snapback Performance for High-Voltage Output ESD Protection

Abstract

A novel high trigger current NPN transistor (HTC-NPN) with excellent double-snapback performance is developed in $0.5\mu \text{m}$ Bipolar CMOS DMOS (BCD) technology. A new floating N+ (FN) layer fabricated in drift-region not only induces two-stage snapback, but also achieves high trigger current ( ${I}_{\text {tr}}$ ) to provide ESD protection for high-voltage (HV) output port without being accidentally triggered on and latch-up like. The operational mechanism and the applied range of the HTC-NPN are discussed in detail, and the double-snapback process induced by the FN is explained via T-CAD simulation as well. From transmission line pulse (TLP) tested results, the proposed HTC-NPN achieved high ${I}_{\text {tr}}$ up to 1.5 A and controllable double-snapback characteristic, thus matching load line from HV output circuit well.