Abstract
In this paper, a high throughput, reduced hardware digital delta sigma modulator (DDSM) for fractional frequency synthesizer is presented. To increase the throughput of DDSM, a special bus splitting scheme is applied which consists of a first order error feedback modulator in prior stage and a third order delta sigma modulator using concentrator in subsequent stage. The concentrator reduces the bits number of the modulator output to 1. The single bit output used in the last stage of proposed structure makes it useful as dual modulus divider (DMD) controller in fractional frequency synthesizer. The proposed structure is implemented on Xilinx Virtex 5 FPGA and yields 104 dB SNR while the required hardware is reduced compared to the previous works.
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