Abstract

Polar code has been proven to achieve the symmetric capacity of memoryless channels. However, the successive cancellation decoding algorithm is inherent serial in nature, which will lead to high latency and low throughput. In order to obtain high throughput, we design a deeply pipelined polar decoder and optimize the processing elements and storage structure. We also propose an improved fixed-point nonuniform quantization scheme, and it is close to the floating-point performance. Two-level control strategy is presented to simplify the controller. In addition, we adopt FIFO structure to implement the α_memory and β_memory and propose the 348-stage pipeline decoder.

Highlights

  • Wireless communication is changing our life and has been applied to many scenarios [1,2,3,4,5], and error-correcting codes are utilized to improve its transmission efficiency and reliability

  • For the ultra-reliable lowlatency communications (URLLC), it should satisfy the high throughput of several tens Gbps [7], which bring in a challenge for polar decoder

  • We investigate the characters of LLRs for different stages of Fast-successive cancellation (SSC) polar decoder and propose an improved nonuniform fixed-point quantization method

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Summary

Introduction

Wireless communication is changing our life and has been applied to many scenarios [1,2,3,4,5], and error-correcting codes are utilized to improve its transmission efficiency and reliability. Polar codes can theoretically achieve channel capacity when code length is infinite, the performance of SC is mediocre for codes of short and moderate lengths To address this issue, successive cancellation list (SCL) decoding algorithm is proposed in [8]. Sarkis proposes the fast simplified successive cancellation (Fast-SSC) decoding algorithm, which mainly improves the decoding rules of Rate-R nodes and gives the specific operation for each constituent node [17]. We investigate the characters of LLRs for different stages of Fast-SSC polar decoder and propose an improved nonuniform fixed-point quantization method. It adopts (6,5,1) quantization scheme; the decoding performance is close to the floating-point decoding performance.

Review of Fast-SSC
Architecture of Fast-SSC Decoder
Performance Analysis
Findings
Conclusions
Full Text
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